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K9F6408U0A-TCB0, K9F6408U0A-TIB0
Document Title
8M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 0.1 0.2 Initial issue. 1. Revised real-time map-out algorithm(refer to technical notes) Changed device name 1) KM29U64000AT -> K9F6408U0A-TCB0 2) KM29U64000AIT -> K9F6408U0A-TIB0 Changed the following items
ITEM Program Time Number of partial program in the same page Before(M-die) 1,000us(Max.) 10 Cycles After(A-die) 500us(Max.) Main Array: 2 Cycles Spare Array: 3 Cycles
Draft Date
April 10th 1999 July 23th 1999 Sep. 15th 1999
Remark
Preliminary Preliminary Preliminary
0.3
Changed the following items
ITEM Pin Configuration(23th Pin) Absolute maximum Ratings - Voltage on any pin relative to Vss Recommended operating conditions - Supply voltage Before(M-die) VccQ Vin : -0.6V to 6V Vcc : -0.6V to 4.6V VccQ : -0.6V to 6V VccQ : 2.7V(Min.) / 5.5V(Max.) I/O pins : 2.0V(Min.) VccQ+0.3V(Max.) Except I/O pins : 2.0V(Min.) / Vcc+0.3V(Max.) 0.8V and 2.0V After(A-die) Vcc Vin : -0.6V to 4.6V Vcc : -0.6V to 4.6V
Oct. 20th 1999
Preliminary
Do not support VccQ
DC and operating characteristics - Input high voltage(VIH)
All inputs : 2.0V(Min.) / Vcc+0.3V(Max.)
Input and output timing levels
1.5V
0.4
Changed the following item
ITEM Data transfer from Cell to Register (tR) Before(M-die) 7us(Max.) After(A-die) 10us(Max.)
Jan. 10th 2000
Final
0.5
1. Changed invalid block(s) marking method prior to shipping - The invalid block(s) information is written the 1st or 2nd page of the invalid block(s) with 00h data --->The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh data at the column address of 517. 2. Changed SE pin description - SE is recommended to coupled to GND or Vcc and should not be toggled during reading or programming.
July 17th 2000
Note : For more detailed features and specifications including FAQ, please refer to Samsung' Flash web site. s http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
8M x 8 Bit NAND Flash Memory
FEATURES
* Voltage Supply : 2.7V ~ 3.6V * Organization - Memory Cell Array : (8M + 256K)bit x 8bit - Data Register : (512 + 16)bit x8bit * Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (8K + 256)Byte * 528-Byte Page Read Operation - Random Access : 10s(Max.) - Serial Page Access : 50ns(Min.) * Fast Write Cycle Time - Program Time : 200s(Typ.) - Block Erase Time : 2ms(Typ.) * Command/Address/Data Multiplexed I/O port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 1Million Program/Erase Cycles - Data Retention : 10 years * Command Register Operation * 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
FLASH MEMORY
GENERAL DESCRIPTION
The K9F6408U0A is a 8M(8,388,608)x8bit NAND Flash Memory with a spare 256K(262,144)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 528-byte page in typically 200s and an erase operation can be performed in typically 2ms on an 8K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9F6408U0As extended reliability of 1,000,000 program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by systemlevel ECC. The K9F6408U0A is an optimum solution for large nonvolatile storage applications such as solid state file storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility.
PIN CONFIGURATION
PIN DESCRIPTION
VSS CLE ALE WE WP N.C N.C N.C N.C N.C
N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
VCC CE RE R/B SE N.C N.C N.C N.C N.C
Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP SE R/B VCC VSS N.C
Pin Function Data Input/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Spare area Enable Ready/Busy output Power Ground No Connection
N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 VCC
44(40) TSOP (II) STANDARD TYPE
NOTE : Connect all VCC and VSS pins of each device to power supply outputs. Do not leave VCC or VSS disconnected.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC VSS A9 - A22 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Y-Gating
FLASH MEMORY
2nd half Page Register & S/A 64M + 2M Bit NAND Flash ARRAY (512 + 16)Byte x 16384 1st half Page Register & S/A
A0 - A7
A8 Command Command Register
Y-Gating
I/O Buffers & Latches VSS
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
Output Driver
I/0 0 I/0 7
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block =16 Pages = (8K + 256) Bytes
16K Pages (=1024 Blocks)
1st half Page Register (=256 Bytes)
2nd half Page Register (=256 Bytes)
1 Page = 528 Bytes 1 Block = 528 Bytes x 16 Pages = (8K + 256) Bytes 1 Device = 528 Bytes x 16Pages x 1024 Blocks = 66 Mbits 8 bit 16 Bytes
512Bytes
Page Register 512 Bytes
I/O 0 ~ I/O 7 16 Bytes
I/O 0 1st Cycle 2nd Cycle 3rd Cycle A0 A9 A17
I/O 1 A1 A10 A18
I/O 2 A2 A11 A19
I/O 3 A3 A12 A20
I/O 4 A4 A13 A21
I/O 5 A5 A14 A22
I/O 6 A6 A15 *X
I/O 7 A7 A16 *X Column Address Row Address (Page Address)
NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * X can be High or Low.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
PRODUCT INTRODUCTION
FLASH MEMORY
The K9F6408U0A is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F6408U0A. The K9F6408U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address loading. The 8M byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F6408U0A.
Table 1. COMMAND SETS
Function Read 1 Read 2 Read ID Reset Page Program Block Erase Read Status 1st. Cycle 00h/01h 50h
(2) (1)
2nd. Cycle 10h D0h -
Acceptable Command during Busy
90h FFh 80h 60h 70h
O
O
NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. The 50h command is valid only when the SE(pin 40) is low level.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
PIN DESCRIPTION
Command Latch Enable(CLE)
FLASH MEMORY
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.
Spare Area Enable(SE)
The SE input controls the access of the spare area. When SE is high, the spare area is not accessible for reading or programming. SE is recommended to be coupled to GND or Vcc and should not be toggled during reading or programming.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS KM29U64000AT KM29U64000AIT Storage Temperature TSTG Symbol VIN VCC Temperature Under Bias TBIAS Rating
FLASH MEMORY
Unit V V C C
-0.6 to + 4.6 -0.6 to + 4.6 -10 to + 125 -40 to + 125 -65 to + 150
NOTE : 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F6408U0A-TCB0:TA=0 to 70C, K9F6408U0A-TIB0:TA=-40 to 85C)
Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7 0 Typ. 3.3 0 Max 3.6 0 Unit V V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Operating Current Sequential Read Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage,All inputs Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL(R/B) IOH=-400A IOL=2.1mA VOL=0.4V Test Conditions tRC=50ns,CE=VIL, IOUT=0mA CE=VIH, WP=SE=0V/VCC CE=VCC-0.2, WP=SE=0V/VCC VIN=0 to 3.6V VOUT=0 to 3.6V Min 2.0 -0.3 2.4 8 Typ 10 10 10 10 10 Max 20 20 20 1 50 10 10 VCC+0.3 0.8 0.4 mA V A mA Unit
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
VALID BLOCK
Parameter Valid Block Number Symbol NVB Min 1014 Typ. 1020
FLASH MEMORY
Max 1024 Unit Blocks
NOTE : 1. The K9F6408U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block.
AC TEST CONDITION
(K9F6408U0A-TCB0:TA=0 to 70C, K9F6408U0A-TIB0:TA=-40 to 85C, VCC=2.7V~3.6V unless otherwise noted)
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (3.0V +/-10%) Output Load (3.3V +/-10%) Value 0.4V to 2.4V 5ns 1.5V 1 TTL GATE and CL = 50pF 1 TTL GATE and CL = 100pF
CAPACITANCE(TA=25C, VCC=3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 10 10 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L L X X X X ALE L H L H L L L X X X(1) X CE L L L L L L L X X X H H H X X X X H X X X X WE RE H H H H H SE X X X X L/H L/H
(3) (3)
WP X X H H H X X H H L Read Mode
Mode Command Input Address Input(3clock) Command Input Address Input(3clock)
Write Mode Data Input
Sequential Read & Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect
L/H(3) L/H(3) X X
0V/VCC(2) 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. 3. When SE is high, spare area is deselected.
Program/Erase Characteristics
Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol tPROG Nop tBERS Min Typ 200 2 Max 500 2 3 4 Unit s cycles cycles ms
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 0 10 0 10 25 0 10 20 10 50 15
FLASH MEMORY
Max Unit ns ns ns ns ns ns ns ns ns ns ns
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay( ID read ) ALE to RE Delay(Read cycle) CE to RE Delay( ID read) Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High Hold Time Output Hi-Z to RE Low Last RE High to Busy(at sequential read) CE High to Ready(in case of interception by CE at read) CE High Hold Time(at the last serial read) (2) RE Low to Status Output CE Low to Status Output WE High to RE Low RE access time(Read ID) Device Resetting Time(Read/Program/Erase) Symbol tR tAR1 tAR2 tCR tRR tRP tWB tRC tREA tRHZ tCHZ tREH tIR tRB tCRY tCEH tRSTO tCSTO tWHR tREADID tRST Min 100 50 100 20 30 50 15 15 0 100 60 Max 10 100 35 30 20 100 50 +tr(R/B) 35 45 35 5/10/500
(1)
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
NAND Flash Technical Notes
Invalid Block(s)
FLASH MEMORY
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to be a valid block.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address Check "FFh" at the column address 517 of the 1st and 2nd page in the block
Create (or update) Invalid Block(s) Table
No
Check "FFh" ?
*
Yes No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
NAND Flash Technical Notes (Continued)
Error in write or read operation
FLASH MEMORY
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Erase Failure Write Program Failure Single Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement or ECC Correction Verify ECC -> ECC Correction
Read
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification operation is not needed. Start Write 00h
Write 80h
Write Address
Write Address
Write Data
Wait for tR Time
Write 10h
Verify Data
No
*
Program Error
Read Status Registe
Yes Program Completed
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
*
*
Program Error
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
Yes
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
FLASH MEMORY
Read Flow Chart
Start Write 00h Write Address Read Data ECC Generation
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed
No
Reclaim the Error
No
Verify ECC Yes Page Read Completed
*
Erase Error
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
Buffer memory
error occurs Page a Block A When the error happens with page "a" of Block "A", try to write the data into another Block "B" from an external buffer. Then, prevent further system access to Block "A" (by creating a "invalid block" table or other appropriate scheme.)
Block B
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
Pointer Operation of K9F6408U0A
FLASH MEMORY
The K9F6408U0A has three modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01h" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations.
"A" area (00h plane)
"B" area (01h plane) 256 Byte
"C" area (50h plane) 16 Byte
Table 1. Destination of the pointer Command 00h 01h 50h Pointer position 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte Area 1st half array(A) 2nd half array(B) spare array(C)
256 Byte
"A"
"B"
"C" Internal Page Register
Pointer select commnad (00h, 01h, 50h)
Pointer
Figure 2. Block Diagram of Pointer Operation
Example of Programming with successive Pointer Operation (1) "A" area program
50h "C" area 00h "A" area 80h
Address / Data input 10h "A" area program 80h
Address / Data input 10h "A" area program
(2) "B" area program
00h "A" area 01h "B" area 80h
Address / Data input 10h "B" area program 80h
Address / Data input 10h "A" area program
(3) "C" area program
00h "A" area 50h "C" area 80h
Address / Data input 10h "C" area program 80h
Address / Data input 10h "C" area program
Table 2. Pointer Status after each operation
Operation Program Pointer status after operation With previous 00h, Device is set to 00h Plane With previous 01h, Device is set to 00h Plane* With previous 50h, Device is set to 50h Plane "00h" Plane("A" area) "00h" Plane("A" area)
Reset Power up
* 01h command is valid just one time when it is used as a pointer for program/erase.
* Erase operation does not affect the pointer status. Previous pointer status is maintained.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
System Interface Using CE don' t-care.
FLASH MEMORY
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 3. Program Operation with CE don' t-care. CLE
CE don' t-care
CE
WE ALE
I/O0~7
80h
Start Add.(3Cycle)
Data Input
Data Input
10h
(Min. 10ns)
tCS CE
(Max. 45ns)
tCH CE
tCEA
tREA tWP WE I/O0~7
Timing requirements : If CE is is exerted high during data-loading, tCS must be minimum 10ns and tWC must be increased accordingly.
RE
out
Timing requirements : If CE is is exerted high during sequential data-reading, the falling edge of CE to valid data(tCEA) must be kept greater than 45ns.
Figure 4. Read Operation with CE don' t-care.
CLE
CE don' t-care Must be held low during tR.
CE
RE ALE R/B tR
WE
I/O0~7
00h
Start Add.(3Cycle)
Data Output(sequential)
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
* Command Latch Cycle
FLASH MEMORY
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/O0 ~ 7
tALH
tDH
Command
* Address Latch Cycle
CLE
tCS CE
tWC
tWC
tWP WE tCLS tALS ALE tDS I/O0 ~ 7 tDH tWH
tWP tWH
tWP
tALH
tDS
tDH
tDS
tDH
A0~A7
A9~A16
A17~A22
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
* Input Data Latch Cycle
tCLH CLE
FLASH MEMORY
tCH CE
tALS ALE
tWC
tWP WE tDS I/O0 ~ 7 tWH tDH
tWP
tDH
tWP tDH
tDS
tDS
DIN 0
DIN 1
DIN 511
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
CE tRP tREA RE
tRC tREH tREA tREA
tCHZ*
tRHZ tRHZ*
I/O0 ~ 7
tRR R/B
Dout
Dout
Dout
NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
* Status Read Cycle
tCLS CLE tCLS tCS CE tCH tWP WE tCSTO tWHR RE tDS I/O0 ~ 7 70h tDH tIR tCLH
FLASH MEMORY
tCHZ
tRSTO tRHZ Status Output
READ1 OPERATION(READ ONE PAGE)
CLE tCEH CE tWC WE tWB tAR2 ALE tR RE tRR I/O0 ~ 7
00h or 01h
tCHZ
tCRY tRHZ
tRC
A0 ~ A7
A9 ~ A16
A17 ~ A22
Dout N
Dout N+1
Dout N+2
Dout N+3
Dout 527
Column Address
Page(Row) Address Busy
tRB
R/B
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K9F6408U0A-TCB0, K9F6408U0A-TIB0
READ1 OPERATION(INTERCEPTED BY CE)
FLASH MEMORY
CLE
CE
WE tWB tAR2 ALE tR RE tRR I/O0 ~ 7
00h or 01h
tCHZ
tRC
A0 ~ A7
A9 ~ A16
A17 ~ A22
Dout N
Dout N+1
Dout N+2
Dout N+3
Column Address
Page(Row) Address Busy
R/B
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE tWB
tR tAR2
ALE tRR
I/O0 ~ 7
50h
A0 ~ A7
A9 ~ A16 A17 ~ A22
Dout 511+M
Dout 511+M+1
RE
Dout 527
R/B M Address
A0 ~ A3 :Valid Address A4 ~ A7 :Dont care
Selected Row
512
16 Start address M
17
K9F6408U0A-TCB0, K9F6408U0A-TIB0
SEQUENTIAL ROW READ OPERATION
FLASH MEMORY
CLE
CE
WE
ALE
RE
I/O0 ~ 7
00h
A0 ~ A7 A9 ~ A16 A17 ~ A22
Dout N
Dout N+1
Dout N+2
Dout 527 Dout 0 Dout 1 Dout 2 Dout 527
R/B
M
Busy
Busy
M+1
N
Output
PAGE PROGRAM OPERATION
CLE
CE tWC WE tWB ALE tPROG tWC tWC
RE
Din Din Din 10h 527 N N+1 1 up to 528 Byte Data Program Sequential Input Command
I/O0 ~ 7
80h
A0 ~ A7 A9 ~ A16 A17 ~ A22 Page(Row) Address
70h Read Status Command
Output I/O0
Sequential Data Column Input Command Address
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
18
K9F6408U0A-TCB0, K9F6408U0A-TIB0
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
FLASH MEMORY
CLE
CE tWC WE tWB ALE tBERS tWC
RE
I/O0 ~ 7
60h
A9 ~ A16 A17 ~ A22 Block Address
DOh
70h
I/O0
Auto Block Erase Setup Command
Erase Command
R/B
Busy
Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
RE tREADID I/O0 ~ 7
90h Read ID Command 00h Address 1st Cycle ECh Maker Code E6h Device Code
19
K9F6408U0A-TCB0, K9F6408U0A-TIB0
DEVICE OPERATION
PAGE READ
FLASH MEMORY
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10s(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address(column 511 or 527 depending on the state of SE pin). After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10s again allows reading the selected page.The sequential row read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command with SE pin low. Toggling SE during operation is prohibited. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each read operation.
Figure 3. Read1 Operation CLE CE WE ALE tR R/B RE I/O0 ~ 7
00h 01h Start Add.(3Cycle) A0 ~ A7 & A9 ~ A22 Data Output(Sequential)
(00h Command)
1st half array 2nd half array
(01h Command)*
1st half array 2nd half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
20
K9F6408U0A-TCB0, K9F6408U0A-TIB0
Figure 4. Read2 Operation CLE CE WE ALE tR R/B RE I/O0 ~ 7
50h Start Add.(3Cycle)
FLASH MEMORY
Data Output(Sequential) Spare Field
1st half array 2nd half array
A0 ~ A3 & A9 ~ A22 (A4 ~ A7 : Don't Care)
Data Field
Spare Field
Figure 5. Sequential Row Read1 Operation tR R/B I/O0 ~ 7 tR
tR
00h 01h
Start Add.(3Cycle) A0 ~ A7 & A9 ~ A22
Data Output 1st
Data Output 2nd (528 Byte)
Data Output Nth (528 Byte) (SE=H, 00h Command)
1st half array 2nd half array
(SE=L, 00h Command)
1st half array 2nd half array
(SE=L, 01h Command)
1st half array 2nd half array
1st 2nd
1st 2nd
1st 2nd
Nth
Nth
Nth
Data Field
Spare Field
Data Field
Spare Field
Data Field
Spare Field
21
K9F6408U0A-TCB0, K9F6408U0A-TIB0
Figure 6. Sequential Row Read2 Operation(SE=fixed low)
FLASH MEMORY
tR R/B I/O0 ~ 7
50h Start Add.(3Cycle) A0 ~ A3 & A9 ~ A22 (A4 ~ A7 : Dont Care)
1st half array 2nd half array
tR
tR
Data Output 1st
Data Output 2nd (16 Byte)
Data Output Nth (16 Byte)
1st 2nd
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 7. Program & Read Status Operation
tPROG R/B I/O0 ~ 7
80h
Address & Data Input A0 ~ A7 & A9 ~ A22 528 Byte Data
10h
70h
I/O0
Pass
Fail
22
K9F6408U0A-TCB0, K9F6408U0A-TIB0
BLOCK ERASE
FLASH MEMORY
The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A13 to A22 is valid while A9 to A12 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 8 details the sequence.
Figure 8. Block Erase Operation tBERS
R/B I/O0 ~ 7
60h
Address Input(2Cycle) Block Add. : A9 ~ A22
D0h
70h
I/O0
Pass
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table2. Read Status Register Definition
I/O # I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Device Operation Write Protect Reserved for Future Use Status Program / Erase Definition "0" : Successful Program / Erase "1" : Error in Program / Erase "0" "0" "0" "0" "0" "0" : Busy "0" : Protected "1" : Ready "1" : Not Protected
23
K9F6408U0A-TCB0, K9F6408U0A-TIB0
READ ID
FLASH MEMORY
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (E6h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CLE tCR CE WE ALE RE I/O0 ~ 7 tREADID
90h 00h Address. 1 cycle ECh Maker code E6h Device code
tAR1
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to "1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation tRST R/B I/O0 ~ 7
FFh
Table3. Device Status
After Power-up Operation Mode Read 1 After Reset Waiting for next command
24
K9F6408U0A-TCB0, K9F6408U0A-TIB0
READY/BUSY
FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper operation and the value may be calculated by the following equation.
Rp VCC
VCC(Max.) - VOL(Max.) R/B open drain output Rp = IOL + IL =
3.2V 8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin.
GND Device
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional software protection.
Figure 11. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
WP
25
High
Package Dimensions
PACKAGE DIMENSIONS
44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F
FLASH MEMORY
Unit :mm/Inch
0~8 0.25 0.010 TYP #44(40) #23(21) 0.45~0.75 0.018~0.030 11.760.20 0.4630.008 10.16 0.400 0.50 0.020 #1 #22(20)
+0.10
0.15 -0.05 0.006 -0.002
+0.004
18.410.10 0.7250.004
1.000.10 0.0390.004
1.20 Max. 0.047
18.81 Max. 0.741
0.10 MAX 0.004 0.05 Min. 0.002
(
0.805 ) 0.032
0.350.10 0.0140.004
0.80 0.0315
26

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